Compiler Strategies for Transport Triggered Architectures
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منابع مشابه
Evaluating transport triggered architectures for scalar applications
In transport triggered architectures (TTAs) the programming and operational model is mirrored when compared with regular RISC and VLIW architectures; instead of programming operations which cause data transports as side eeects, in TTAs the transports are programmed, where a transport may trigger an operation if necessary. Transports are therefore visible at the architecture level, and are compl...
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The paper describes how resource assignment is performed in a compiler for transport triggered architectures, and in particular, how busses are assigned to data transports. This becomes an important issue when function units and register files are only partially interconnected via an irregular network of busses. Reducing this connectivity is important for processors exploiting instruction level...
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The trend in programmable architectures for digital signal processing (DSP) is to move towards high-level language programming, which sets high requirements for compilers to efficiently exploit the instruction level parallelism in modern processors. In this paper, efficiency of transport triggered architectures (TTA) in DSP applications is discussed. The efficiency of a high-level compiler on a...
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A functional language compiler can be used as a powerful tool in the scheduling of programs for hardware capable of ne grained instruction level parallelism. There have been many attempts to eeectively utilise functional languages as a means of easily programming parallel hardware. These attempts have generally concentrated on parallelising the underlying reduction strategies to achieve this go...
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This paper reports the results of a comparison between a new class of architectures, called transport-triggered architectures, and traditional architectures, called operation-t~iggered architectures. It does this comparison by means of the MOVE-i860, which is a transport-triggered approximation of the i860. Several benchmarks are scheduled for the MOVE-i860 by a software pipelining scheduler. B...
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تاریخ انتشار 2001